Test Scheduling and Test Time Reduction for SoC by Using Enhanced Firefly Algorithm

System-on-Chip (SoC) is an integration of electronic components and billions transistors. Defects due to the base material caused during manufacturing components. To overcome these issues testing chips necessary but total cost increases because increasing test time. The main be considered SoC are time taken for accessibility core. Effective scheduling should done minimize In this paper, effective mechanism proposed. reduction causes reduction. Enhanced Firefly algorithm used in paper gives a better result than Ant colony algorithms terms thereby takes place.